(a) Field of the Invention
The present invention relates to a bus request signal mediating circuit and, more particularly, to a bus request signal mediating circuit for mediating between a plurality of bus accessing circuits sharing a single bus line.
(b) Description of the Related Art
When a single bus is shared among a plurality of bus accessing circuit, a bus request signal mediating circuit is generally used for mediating the use of the single bus by the plurality of accessing circuits. An example of such a bus request signal mediating circuit is described in JP-A-4(1992)-52749.
FIG. 1 shows the bus request signal mediating circuit described in the publication mentioned above. The bus request signal mediating circuit is provided for mediating between three accessing circuits 14, 15 and 16, and comprises a first register section 401 for latching bus request signals 101, 102 and 103, a selector 402 for selecting one of the bus request signals from first register section 401 based on a control signal 407 specifying the address of first register section 401, a RAM 403 for storing the priority data between the bus request signals in memory cells which are accessed by the address specified by an output from selector 402, and a second register section 404 for latching outputs from RAM 403 to deliver a bus use authorization signal to one of the bus accessing circuits 14, 15 and 16.
When any number of accessing circuits 14, 15 and 16 output bus request signals 101, 102 and/or 103, the bus request signals are latched by first register section 401 and input to RAM 403 through selector 402 as an address signal for RAM 403. RAM 403 delivers an authorization signal 104, 105 or 106 to one of accessing circuits 14, 15 and 16 through register 404 based on the bus request signals and the priority stored in RAM 403 among the bus request signals 101, 102 and 103.
An OR gate 406 suppresses an output from first register section 401 while second register section 404 delivers the authorization signal, thereby suppressing further inputs from other accessing circuits. After the specified accessing circuit finishes the processing using bus line 12, OR gate 405 delivers an end signal to reset register 404, which enables further mediating operation between the bus request signals 101, 102 and 103. The priority data stored in RAM 403 can be updated by a new priority data 409, which is supplied from outside the mediating circuit by using a control signal 408 to switch the input of selector 402 to an address signal 407.
The bus request signal mediating circuit as described above has a problem in that if the highest priority accessing circuit outputs the accessing signal in succession, the bus line cannot be used by other lower priority accessing circuits, resulting in monopoly of the single bus by the highest priority accessing circuit.
In addition, if the number of accessing circuits increases due to a complicated circuit configuration, update of the priority data consumes a large amount of time due to a large number of bits to be stored in the RAM.